1. Field of the Invention
The present invention relates to an intermediate chip for electrically connecting semiconductor chips, and relates to a semiconductor device, a circuit board, and an electronic device having semiconductor chips electrically connected by means of such an intermediate chip. The present invention also relates to an intermediate chip module, a semiconductor device, a circuit board, and an electronic device.
2. Description of Related Art
Currently, efforts are being made to reduce the size of electronic components (e.g., semiconductor chips) used in mobile electronic devices, such as portable telephones, notebook personal computers, PDAs (Personal Data Assistants) in general, so that the size and weight of such devices are reduced. Spaces for mounting such electronic components are also limited. To achieve this, various methods for packaging semiconductor chips, for example, have been conceived of, and a packaging, known as CSP (chip scale package) is proposed at present. High-density packaging can be achieved with the CSP technique since the mounting areas of semiconductor chips which are manufactured using this CSP technique are comparable to those of conventional semiconductor chips.
In addition, a further reduction in size of and provision of multiple functions to the above-mentioned electronic devices are anticipated, and further increase in packaging density of semiconductor chips is required. In view of the above-mentioned background, a three-dimensional chip stacking technique has been proposed. The three-dimensional chip stacking technique achieves high-density packaging of semiconductor chips by stacking semiconductor chips having similar and/or different functions together and connecting them together via wiring (see, for example, Japanese Unexamined Patent Nos. 2002-170919 and 2002-100727).
In the three-dimensional chip stacking technique, increasing density of semiconductor chips has reduced pitches between terminals, making connection between the terminals and outside terminal difficult. Thus, a redistribution layer is required.
However, since all junctions of semiconductor chips are provided at the same position in the technique disclosed in JP 2002-170919, a redistribution layer cannot be achieved solely by this technique. On the other hand, in the technique disclosed in JP 2002-100727, wiring can be redistributed on a semiconductor chip to facilitate connection to outside terminals. However, since an additional wiring is added to a semiconductor circuit, the manufacturing process becomes complex, and the yield is reduced.
In the three-dimensional chip stacking technique, a redistribution layer is required for disposing pads and for stacking different kind of chips having different die sizes. Furthermore, a technique for easily manufacturing three-dimensional chips which simplify handling of the chips without incurring a decrease in yields has been desired. Furthermore, a technique which enhances flexibility in design and structure of three-dimensional stacked chips as well as easily allows for enhancement of characteristics of semiconductor devices has been also desired.